
	GET s2c2440_addr.inc
	GET Memcfg.inc

	IMPORT isr_eint4_7

U_MDIV		EQU	56		;Fin=12.0MHz Fout=48MHz
U_PDIV		EQU	2
U_SDIV		EQU	2

M_MDIV		EQU	173
M_PDIV		EQU	2
M_SDIV		EQU	2

OFFSET_EINT4_7 EQU	4

USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b
MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

_STACK_BASEADDRESS	EQU 0x33ff8000

UserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~
SVCStack	EQU	(_STACK_BASEADDRESS-0x2800)	;0x33ff5800 ~
UndefStack	EQU	(_STACK_BASEADDRESS-0x2400)	;0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000)	;0x33ff6000 ~
IRQStack	EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~


	
	AREA asm,CODE,READONLY
	ENTRY



start
	;disable watchdog
	ldr r0, =0x53000000
	mov r1, #0
	str r1, [r0]

	;diable all interrupt
	ldr r0, =0x4a000008
	ldr r1, =0xffffffff
	str r1, [r0]

	;diable all sub interrupt
	ldr r0, =0x4a00001c
	ldr r1, =0x7fff
	str r1, [r0]

	;adjust PLL time
	ldr r0, =0x4c000000
	ldr r1, =0xffffff
	str r1, [r0]

	;confirm clock divide
	;Fclk:Hclk:Pclk
	ldr r0, =0x4c000014
	ldr r1, =0x7	;0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6
	str r1, [r0]

	ldr r0, =0x4c000008
	ldr r1, =((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
	str r1, [r0]

	;Configure MPLL
	ldr	r0,=0x4c000004
	ldr	r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) 
	str	r1,[r0]

	nop	; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
	nop
	nop
	nop
	nop
	nop
	nop 

	;Check if the boot is caused by the wake-up from SLEEP mode.
	ldr	r1,=0x560000b4
	ldr	r0,[r1]
	tst	r0,#0x2
	;bne	WAKEUP_SLEEP

	;Set memory control registers
 	ldr	r0,=SMRDATA
	ldr	r1,=0x48000000
	add	r2, r0, #52	;End address of SMRDATA

0
	ldr r3, [r0], #4
	str r3, [r1], #4
	cmp r2, r0
	bne %B0

	bl init_stacks

	;set eint4_7 isr routine
	ldr r0, =OFFSET_EINT4_7
	ldr r1, =isr_eint4_7
	str r1, [r0]



init_stacks
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack		; UndefStack=0x33FF_5C00

	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack		; AbortStack=0x33FF_6000

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack		; IRQStack=0x33FF_7000

	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack		; FIQStack=0x33FF_8000

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack		; SVCStack=0x33FF_5800

	mov	pc,lr

SMRDATA DATA
	DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    													;GCS6
	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    													;GCS7
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
	DCD 0x32	    ;SCLK power saving mode, BANKSIZE 128M/128M
	DCD 0x30	    ;MRSR6 CL=3clk
	DCD 0x30	    ;MRSR7 CL=3clk 



	END